An improved interface circuit for allowing data to be transmitted between two data busses wherein the interface contains a FIFO buffer per channel for transmitting the data in either direction, and wherein the operation of the buffers can be frozen at a point in time to allow the CPU to inspect, and to modify if necessary, the data in the control circuit and buffers prior to enabling the buffers to resume regular operation.
In normal computer systems which process data in the form of numbers or character coded text, the data rate is usually modest, perhaps eight bits for a character and four bits for a numerical digit, resulting in thousands of bits per page. In this case the system is normally able to process the data in the software. However, in systems that process images, the data rates are very high, easily reaching up into the millions of bits per page, and to allow the computer to keep up with the printer speed, "accelerator" cards are frequently used. These are specially designed hardware circuits which accomplish specific image handling functions such as compression, decompression and image rotation.
Normally, these accelerator cards are extra circuit boards which may be plugged into the CPU backplane and transmit data over the existing data bus. However, in high speed systems the amount of data transmitted between accelerator cards overloads the data bus. One solution is to provide a separate data bus for the accelerator cards, herein called a local, or "L" bus, in addition to the system, or "S" bus. Then, between these two busses there must be an interface circuit.
It frequently happens that after data is decompressed or rotated, it will be sent to a printer. Similarly, data received from a scanner may be compressed. Therefore, from a system optimization viewpoint, it is appropriate that I/O devices such as the scanner and printer also be connected to the L bus.
On the other hand, the printer may operate at much higher speeds than does the disk and scanner. In this case, large amounts of data must be temporarily stored in the main CPU memory prior to printing. This necessitates the frequent transmission of large amounts of image data across the interface circuit between the L bus and the S bus.
A common problem with this kind of interface circuit is that it is handling large amounts of data in two directions based on instructions from various cards, and it may, under certain conditions, either be handling the data improperly or not in the most optimum way. An example of the first condition is where the system has a fault, and the maintenance person is trying to find out where the fault is occurring. An example of the second is where the interface is instructed that the following transmission is the output of the compressor. Since the compression ratio is variable, the length of the transmission is not known beforehand. Therefore, when requesting a transmission, the compressor card will assume a worst case compression ratio of, for example, 1 to 1, and reserve that much time. It would be convenient if the CPU could freeze the interface after half or two thirds of the allotted time has elapsed to see if the transmission has been completed, so that the interface could be used for another purpose.
In prior systems, the stoppage of the interface to inspect the buffer contents has, itself, been a source of faults since any disruption of the data by stopping and starting the buffer will frequently result in lost or displaced data bits. Therefore, the general rule has been that the buffer is never stopped. As explained above, this results in making trouble-shooting more difficult and data transmissions more time consuming.